As Moore’s Law continues its relentless march toward ever smaller geometries on wafer, lithographers who
had been relying on the implementation of a solution using EUV lithography are faced with increasing
challenges to meet requirements for printing sub-2x nm half-pitch (HP). The available choices rely on 193 nm DUV immersion lithography, but with decreasing k1 values and thus shrinking process windows. To overcome these limitations, two techniques such as inverse lithography technology (ILT) and source mask optimization (SMO) were introduced by computational OPC scheme.
From a mask inspection viewpoint, the impact of both ILT and SMO is similar – both result in photomasks that have a large quantity of sub-resolution assist features (SRAFs). These SRAFs are challenging for mask-makers
to pattern with high fidelity and accuracy across a full-field mask, and thus mask inspection is challenged to maintain a high sensitivity level on primary mask features while not suffering from a high nuisance detection rate on the SRAF features. To solve this particular issue, new inspection approach was developed by using computational image calibration based wafer scanner simulation. This paper will be described the new
capabilities, which analyzes the aerial image to differentiate between printing and non-printing features, and
applying the appropriate sensitivity threshold. All analysis will be shown comparing results with and without the
new capabilities, with an emphasis on inspectability improvements and nuisance defect reduction to improve
mask cycle time.