Nanostructures applied to bit-cell devices

Andrzej Kołodziej; Lidia Łukasiak; Michał Kołodziej

doi:10.1117/12.2031301

25 July 2013 Nanostructures applied to bit-cell devices

Andrzej Kołodziej, Lidia Łukasiak, Michał Kołodziej

Proceedings Volume 8902, Electron Technology Conference 2013; 89020X (2013) https://doi.org/10.1117/12.2031301
Event: Electron Technology Conference 2013, 2013, Ryn, Poland

Abstract

In this work split-gate charge trap FLASH memory with a storage layer containing 3D nano-crystals is proposed and compared with existing sub-90 nm solutions. We estimate electrical properties, cell operations and reliability issues. Analytical predictions show that for nano-crystals with the diameter < 3 nm metals could be the preferred material. The presented 3D layers were fabricated in a CMOS compatible process. We also show what kinds of nano-crystal geometries and distributions could be achieved. The study shows that the proposed memory cells have very good program/erase/read characteristics approaching those of SONOS cells but better retention time than standard discrete charge storage cells. Also dense nano-crystal structure should allow 2-bits of information to be stored.

Citation Download Citation

Andrzej Kołodziej, Lidia Łukasiak, and Michał Kołodziej "Nanostructures applied to bit-cell devices", Proc. SPIE 8902, Electron Technology Conference 2013, 89020X (25 July 2013); https://doi.org/10.1117/12.2031301

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