11 September 2013 ROIC for gated 3D imaging LADAR receiver
Author Affiliations +
Proceedings Volume 8907, International Symposium on Photoelectronic Detection and Imaging 2013: Infrared Imaging and Applications; 890748 (2013) https://doi.org/10.1117/12.2034589
Event: ISPDI 2013 - Fifth International Symposium on Photoelectronic Detection and Imaging, 2013, Beijing, China
Time of flight laser range finding, deep space communications and scanning video imaging are three applications requiring very low noise optical receivers to achieve detection of fast and weak optical signal. HgCdTe electrons initiated avalanche photodiodes (e-APDs) in linear multiplication mode is the detector of choice thanks to its high quantum efficiency, high gain at low bias, high bandwidth and low noise factor. In this project, a readout integrated circuit of hybrid e-APD focal plane array (FPA) with 100um pitch for 3D-LADAR was designed for gated optical receiver. The ROIC works at 77K, including unit cell circuit, column-level circuit, timing control, bias circuit and output driver. The unit cell circuit is a key component, which consists of preamplifier, correlated double Sampling (CDS), bias circuit and timing control module. Specially, the preamplifier used the capacitor feedback transimpedance amplifier (CTIA) structure which has two capacitors to offer switchable capacitance for passive/active dual mode imaging. The main circuit of column-level circuit is a precision Multiply-by-Two circuit which is implemented by switched-capacitor circuit. Switched-capacitor circuit is quite suitable for the signal processing of readout integrated circuit (ROIC) due to the working characteristics. The output driver uses a simply unity-gain buffer. Because the signal is amplified in column-level circuit, the amplifier in unity-gain buffer uses a rail-rail amplifier. In active imaging mode, the integration time is 80ns. Integrating current from 200nA to 4uA, this circuit shows the nonlinearity is less than 1%. In passive imaging mode, the integration time is 150ns. Integrating current from 1nA to 20nA shows the nonlinearity less than 1%.
© (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Guoqiang Chen, Guoqiang Chen, Junling Zhang, Junling Zhang, Pan Wang, Pan Wang, Jie Zhou, Jie Zhou, Lei Gao, Lei Gao, Ruijun Ding, Ruijun Ding, "ROIC for gated 3D imaging LADAR receiver", Proc. SPIE 8907, International Symposium on Photoelectronic Detection and Imaging 2013: Infrared Imaging and Applications, 890748 (11 September 2013); doi: 10.1117/12.2034589; https://doi.org/10.1117/12.2034589


Design of a ROIC with high dynamic range for LWIR...
Proceedings of SPIE (November 10 2014)
Analysis and simulation of a new kind of noise at...
Proceedings of SPIE (May 20 2014)
Ultra low noise high frame rate ROIC for visible and...
Proceedings of SPIE (September 28 2004)
0.18 μm CMOS fully differential CTIA for a 32x16 ROIC...
Proceedings of SPIE (September 06 2006)
High gain 0.8 um CMOS readout integrated circuit for FM...
Proceedings of SPIE (October 09 2003)

Back to Top