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21 August 2013 A low-power column-parallel ADC for high-speed CMOS image sensor
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Proceedings Volume 8908, International Symposium on Photoelectronic Detection and Imaging 2013: Imaging Sensors and Applications; 89082E (2013) https://doi.org/10.1117/12.2034924
Event: ISPDI 2013 - Fifth International Symposium on Photoelectronic Detection and Imaging, 2013, Beijing, China
Abstract
This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.
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Ye Han, Quanliang Li, Cong Shi, Liyuan Liu, and Nanjian Wu "A low-power column-parallel ADC for high-speed CMOS image sensor", Proc. SPIE 8908, International Symposium on Photoelectronic Detection and Imaging 2013: Imaging Sensors and Applications, 89082E (21 August 2013); https://doi.org/10.1117/12.2034924
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