8 March 2014 Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures
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Proceedings Volume 8991, Optical Interconnects XIV; 89910Z (2014) https://doi.org/10.1117/12.2042732
Event: SPIE OPTO, 2014, San Francisco, California, United States
Abstract
The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Nikos Pleros, Nikos Pleros, Pavlos Maniotis, Pavlos Maniotis, Theonitsa Alexoudi, Theonitsa Alexoudi, Dimitris Fitsios, Dimitris Fitsios, Christos Vagionas, Christos Vagionas, Sotiris Papaioannou, Sotiris Papaioannou, K. Vyrsokinos, K. Vyrsokinos, George T. Kanellos, George T. Kanellos, } "Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures", Proc. SPIE 8991, Optical Interconnects XIV, 89910Z (8 March 2014); doi: 10.1117/12.2042732; https://doi.org/10.1117/12.2042732
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