4 March 2014 Pixel structure with 10 nsec fully charge transfer time for the 20m frame per second burst CMOS image sensor
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Abstract
In this paper, we demonstrate the technologies related to the pixel structure achieving the fully charge transfer time of less than 10 nsec for the 20M frame per second burst CMOS image sensor. In this image sensor, the size of the photodiode (PD) is 30.0 μmH x 21.3 μmV in the 32.0 μmH x 32.0 μmV pixel. In the pixel, the floating diffusion (FD) and the transfer-gate-electrode (TG) are placed at the bottom center of the PD. The n-layer for the PD consists of the semicircular regions centered on the FD and the sector-shaped portions extending from the edges of the semicircular regions. To generate an electric field greater than the average of 400 V/cm toward the FD direction in the entire PD region, the n-layer width of the sector-shaped portions becomes narrower from the proximal-end to the distal-end. By using the PD structure, which includes the above mentioned n-layer shape and the PD dopant profile with the condition of three times n-type dopant implantation, we achieved to collect 96 % of the charges generated in the PD at the FD within 10 nsec. An ultra-high speed CMOS image sensor with the abovementioned pixel structure has been fabricated. Through the experiments, we confirmed three key characteristics as follows; the image lag was below the measurement limit, the electron transit time in the PD was less than 10 nsec, and the entire PD region had equivalent sensitivity.
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K. Miyauchi, Tohru Takeda, K. Hanzawa, Y. Tochigi, S. Sakai, R. Kuroda, H. Tominaga, R. Hirose, K. Takubo, Y. Kondo, S. Sugawa, "Pixel structure with 10 nsec fully charge transfer time for the 20m frame per second burst CMOS image sensor", Proc. SPIE 9022, Image Sensors and Imaging Systems 2014, 902203 (4 March 2014); doi: 10.1117/12.2042373; https://doi.org/10.1117/12.2042373
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