18 February 2014 Fixed tile rate codec for bandwidth saving in video processors
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Abstract
The paper presents an image compression circuit for bandwidth saving in video display processors. This is intra frame tile based compression algorithm offering visually lossless quality for compression rates between 1.5 and 2.5. RGB and YCbCr (4:4:4, 4:2:2 and 4:2:0) video formats are supported for 8/10 bits video signals. The Band Width Compressor (BWC) consists of Lossless Compressor (LC) and Quantization Compressor (QC) that generate output bit streams for tiles of pixels. Size of output bit stream generated for a tile by the LC may be less or greater than a required size of output memory block. The QC generates bit stream that always fits output memory block of the required size. The output bit stream generated by the LC is transmitted if its size is less than the required size of the output memory block. Otherwise, the output bit stream generated by the QC is transmitted. The LC works on pixel basis. A difference between original and predicted pixel’s values for each pixel of a tile is encoded as prefix and suffix. The prefix is encoded by means of variable length code, and suffix is encoded as is. The QC divides a tile of pixels on a set of blocks and quantizes pixels of each block independently of the other blocks. The number of quantization bits for all pixels of a block depends on standard deviation calculated over the block. A difference between pixel’s value and average value over the block is quantized and transmitted.
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Vladimir Lachine, Vladimir Lachine, Chon-Tam Le Dinh, Chon-Tam Le Dinh, Dinh Kha Le, Dinh Kha Le, Jeffrey Wong, Jeffrey Wong, } "Fixed tile rate codec for bandwidth saving in video processors", Proc. SPIE 9030, Mobile Devices and Multimedia: Enabling Technologies, Algorithms, and Applications 2014, 90300O (18 February 2014); doi: 10.1117/12.2057413; https://doi.org/10.1117/12.2057413
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