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17 April 2014 Pattern fidelity verification for logic design in EUV lithography
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Abstract
We verify image fidelity after mask 3D aware-OPC (using Mentor Graphics Domain Decomposition Method) and quantify pattern placement error (PPE) on wafer. First we show experimental pattern fidelity improvement of DDM-OPCed 2D-images of logic devices in 10 nm technology node with the latest NXE3300B EUV exposure tool. We then compare pattern fidelity in aerial images after DDM-OPC to aerial images using rigorous simulation of electric and magnetic field. Finally we quantify PPE in resist images with modeled 1D layouts after a perfect OPC. The perfect OPC corrects optical proximity effect, azimuthal angle through slit, and lens aberration. The forecasted PPE residual error after perfect OPC is 0.21 nm (x) and 0.76 nm (y) that can be attributed to uncorrectable components of wafer defocus and mask flatness. For modeling and compensation of pattern placement error, a new metrology method should be developed.
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Minoru Sugawara, Eric Hendrickx, Vicky Philipsen, Chris Maloney, and Germain Fenger "Pattern fidelity verification for logic design in EUV lithography", Proc. SPIE 9048, Extreme Ultraviolet (EUV) Lithography V, 90480V (17 April 2014); https://doi.org/10.1117/12.2046096
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