Translator Disclaimer
18 March 2014 Stochastic and systematic patterning failure mechanisms for contact-holes in EUV lithography: Part 2
Author Affiliations +
Patterning uncertainty in EUV lithography arises from each lithographic component: the source, the photomask, the optical system, and the photoresist. All contribute to line roughness and contact disuniformity. In extreme cases, feature variability can result in patterning failures such as line microbridging or random missing contact holes. Historically, redundant contact holes (or vias) were placed to overcome the effects of a missing contact. Due to the aggressive CD shrink of feature size, the use of redundant contacts has been progressively decreased. For some types of devices, almost every contact of the billions found on the chip must be electrically active in order for the device to function. In such scenario, lithographic printing failures may cause catastrophic loss of yield, considering that closed contacts can hardly be corrected by smoothing techniques or etching. In this paper, the minimum contact CD which prints without failure – the contact hole printability limit – is studied for 54nm and 44nm pitch dense arrays. We find that the same resist may show dramatically different printability limits depending upon sizing dose and illumination conditions. This analysis will be implemented to estimate, through simulation-assisted experiments, the required exposure dose and aerial image to safely print sub-30nm contact holes.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Alessandro Vaglio Pret, Peter De Bisschop, Mark D. Smith, and John J. Biafore "Stochastic and systematic patterning failure mechanisms for contact-holes in EUV lithography: Part 2", Proc. SPIE 9048, Extreme Ultraviolet (EUV) Lithography V, 904834 (18 March 2014);


Extension of practical k1 limit in EUV lithography
Proceedings of SPIE (March 17 2016)
Design intent optimization at the beyond 7nm node ...
Proceedings of SPIE (March 29 2017)
Comparison between ADT and PPT for 2X DRAM patterning
Proceedings of SPIE (April 07 2011)
Low-k1 imaging: how low can we go?
Proceedings of SPIE (October 19 2000)

Back to Top