4 December 2016 Making the impossible: dealing with patterns throughout the design and manufacturing flow (Presentation Recording)
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Proceedings Volume 9049, Alternative Lithographic Technologies VI; 90492R (2016); doi: 10.1117/12.2230986
Event: SPIE Advanced Lithography, 2014, San Jose, California, United States
Abstract
We have always described a semiconductor process node by aspects of pitch. Whether it is a minimum channel length, metal spacing, or as seems more common now, a number driven by the marketing department’s target message, everything came down to widths and spaces. Regardless as to how we got there, this matched well with both design and manufacturing views up though about 130nm. For designers, smaller transistors, and smaller interconnect pitches mapped to faster, smaller, and cheaper designs. For the fab, the widths and spaces mapped directly onto particle defect densities and defined their yield challenge. The world started to change somewhere in the 130nm to 90nm timeframe. Driven by the well-known difficulties involved in lithography and exacerbated by increased sensitivity in processes like CMP, design style-based or systematic defects became the major challenge to yieldramp, adding to the basic process ramp. Because of its involvement in the design, manufacturing, and test; EDA is in a unique position to contribute towards controlling, if not solving, the problem. We’ll look at: • Solutions in the DFT space that let us identify pattern failures hiding in yield loss • New methods in OPC that allow for process window expansion of problematic hot spots • Upcoming modeling technologies that target new pattern failure mechanisms in emerging nodes • New tools in the design spaces that can give designers visibility into the risks of production. The goal is a pattern aware EDA flow that minimizes risk, enhances manufacturing and quickly finds issues when they occur.
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Sawicki: Making the impossible: dealing with patterns throughout the design and manufacturing flow (Presentation Recording)

We’ll look at:

  • Solutions in the DFT space that let us identify pattern failures hiding in yield loss

  • New methods in OPC that allow for process window expansion of problematic hot spots

  • Upcoming modeling technologies that target new pattern failure mechanisms in emerging nodes

  • New tools in the design spaces that can give designers visibility into the risks of production.

The goal is a pattern aware EDA flow that minimizes risk, enhances manufacturing and quickly finds issues when they occur.

View presentation video on SPIE’s Digital Library: http://dx.doi.org/10.1117/12.2230986.3257945308001

Joseph D. Sawicki, "Making the impossible: dealing with patterns throughout the design and manufacturing flow (Presentation Recording)", Proc. SPIE 9049, Alternative Lithographic Technologies VI, 90492R (4 December 2016); doi: 10.1117/12.2230986; http://dx.doi.org/10.1117/12.2230986
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KEYWORDS
Manufacturing

Design for manufacturability

Electronic design automation

Lithography

Chemical mechanical planarization

Metals

Optical proximity correction

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