Improvement in electron-beam lithography throughput by exploiting relaxed patterning fidelity requirements with directed self-assembly

Hao Yun Yu; Chun-Hung Liu; Yu Tian Shen; Hsuan-Ping Lee; Kuen Yu Tsai

doi:10.1117/12.2046615

28 March 2014 Improvement in electron-beam lithography throughput by exploiting relaxed patterning fidelity requirements with directed self-assembly

Hao Yun Yu, Chun-Hung Liu, Yu Tian Shen, Hsuan-Ping Lee, Kuen Yu Tsai

Author Affiliations +

Proceedings Volume 9049, Alternative Lithographic Technologies VI; 90492C (2014) https://doi.org/10.1117/12.2046615
Event: SPIE Advanced Lithography, 2014, San Jose, California, United States

Abstract

Line edge roughness (LER) influencing the electrical performance of circuit components is a key challenge for electronbeam lithography (EBL) due to the continuous scaling of technology feature sizes. Controlling LER within an acceptable tolerance that satisfies International Technology Roadmap for Semiconductors requirements while achieving high throughput become a challenging issue. Although lower dosage and more-sensitive resist can be used to improve throughput, they would result in serious LER-related problems because of increasing relative fluctuation in the incident positions of electrons. Directed self-assembly (DSA) is a promising technique to relax LER-related pattern fidelity (PF) requirements because of its self-healing ability, which may benefit throughput. To quantify the potential of throughput improvement in EBL by introducing DSA for post healing, rigorous numerical methods are proposed to simultaneously maximize throughput by adjusting writing parameters of EBL systems subject to relaxed LER-related PF requirements. A fast, continuous model for parameter sweeping and a hybrid model for more accurate patterning prediction are employed for the patterning simulation. The tradeoff between throughput and DSA self-healing ability is investigated. Preliminary results indicate that significant throughput improvements are achievable at certain process conditions.

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Hao Yun Yu, Chun-Hung Liu, Yu Tian Shen, Hsuan-Ping Lee, and Kuen Yu Tsai "Improvement in electron-beam lithography throughput by exploiting relaxed patterning fidelity requirements with directed self-assembly", Proc. SPIE 9049, Alternative Lithographic Technologies VI, 90492C (28 March 2014); https://doi.org/10.1117/12.2046615

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KEYWORDS

Line edge roughness

Critical dimension metrology

Directed self assembly

Electron beam lithography

Lithography

Optical lithography

Transistors

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