2 April 2014 Addressing FinFET metrology challenges in 1X node using tilt-beam CD-SEM
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Abstract
At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R2 being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.
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Xiaoxiao Zhang, Hua Zhou, Zhenhua Ge, Alok Vaid, Deepasree Konduparthi, Carmen Osorio, Stefano Ventola, Roi Meir, Ori Shoval, Roman Kris, Ofer Adan, Maayan Bar-Zvi, "Addressing FinFET metrology challenges in 1X node using tilt-beam CD-SEM", Proc. SPIE 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII, 90500C (2 April 2014); doi: 10.1117/12.2046881; https://doi.org/10.1117/12.2046881
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