Paper
2 April 2014 20nm MOL overlay case study
Lokesh Subramany, Michael Hsieh, Chen Li, Hui Peng Koh, David Cho, Anna Golotsvan, Vidya Ramanathan, Ramkumar Karur Shanmugam, Lipkong Yap
Author Affiliations +
Abstract
As the process nodes continue to shrink, overlay budgets are approaching theoretical performance of the tools. It becomes even more imperative to improve overlay performance in order to maintain the roadmap for advance integrated circuit manufacturing. One of the critical factors in 20nm manufacturing is the overlay performance between the Middle of Line (MOL) and the Poly layer. The margin between these two layers was a process limiter, it was essential that we maintain a very tight overlay control between these layers. Due to various process and metrology related effects, maintaining good overlay control became a challenge. In this paper we describe the various factors affecting overlay performance and the measures taken to mitigate or eliminate said factors to improve overlay performance.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Lokesh Subramany, Michael Hsieh, Chen Li, Hui Peng Koh, David Cho, Anna Golotsvan, Vidya Ramanathan, Ramkumar Karur Shanmugam, and Lipkong Yap "20nm MOL overlay case study", Proc. SPIE 9050, Metrology, Inspection, and Process Control for Microlithography XXVIII, 90502Q (2 April 2014); https://doi.org/10.1117/12.2046598
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KEYWORDS
Overlay metrology

Semiconducting wafers

Chemical mechanical planarization

Optical alignment

Metrology

Image processing

Image quality

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