27 March 2014 Robust complementary technique with multiple-patterning for sub-10 nm node device
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Abstract
Extreme ultraviolet (EUV) lithography is the leading candidate for sub-20nm half-pitch (hp) patterning solution, but the development of a high-output light source is still in progress thereby delaying the adoption of EUV for mass production. The evolution of 193nm immersion lithography-an exposure technology currently used in the mass production of all advanced devices-must therefore be extended, and to this end, self-aligned multiple patterning (SAMP) processes have come to be used to achieve further down scaling. To date, we have demonstrated the effectiveness of self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as innovative processes and have reported on world-first scaling results at SPIE on several occasions. However, for critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for line-cutting techniques (grating and cutting). Under the theme of existing- technology extension to sub-10nm logic nodes, this paper presents the potential solutions of sub-10nm hp resolution by self-aligned octuple patterning (SAOP) and discusses the limits of shrink technology in cutting patterns.
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Kenichi Oyama, Shohei Yamauchi, Sakurako Natori, Arisa Hara, Masatoshi Yamato, Hidetami Yaegashi, "Robust complementary technique with multiple-patterning for sub-10 nm node device", Proc. SPIE 9051, Advances in Patterning Materials and Processes XXXI, 90510V (27 March 2014); doi: 10.1117/12.2046236; https://doi.org/10.1117/12.2046236
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