Paper
27 March 2014 Anti-spacer double patterning
Author Affiliations +
Abstract
With extreme UV not ready for HVM for the 20nm and 14nm nodes, double patterning options that extend the use of 193nm immersion lithography beyond the optical resolution limits, such as LELE (Litho-Etch-Litho-Etch) and SADP (Self Aligned Double Patterning), are being used for critical layers for these nodes. LELE requires very stringent overlay capability of the optical exposure tool. The spacer scheme of SADP starts with a conformal film of material around the mandrels and etched along the mandrel sidewalls to form patterns with doubled frequency. SADP, while having the advantage of being a self-aligned process, adds a number of process steps and strict control of the mandrel profile is required. In this paper, we will demonstrate a novel technique - ASDP (Anti-Spacer Double Patterning), which uses only spin-on materials to achieve self-aligned double patterning. After initial resist patterning, an Anti-Spacer Generator (ASG) material is coated on the resist pattern to create the developable spacer region. Another layer of material is then coated and processed to generate the second pattern in between the first resist pattern. We were able to define 37.5nm half pitch pattern features using this technique as well as sub-resolution features for an asymmetric pattern. In this paper we will review the capability of the process in terms of CD control and LWR (line width roughness) and discuss the limitations of the process.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Michael Hyatt, Karen Huang, Anton DeVilliers, Mark Slezak, and Zhi Liu "Anti-spacer double patterning", Proc. SPIE 9051, Advances in Patterning Materials and Processes XXXI, 905118 (27 March 2014); https://doi.org/10.1117/12.2045617
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Cited by 1 scholarly publication.
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KEYWORDS
Double patterning technology

Line width roughness

Optical lithography

Photoresist processing

Coating

Etching

Semiconducting wafers

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