CMOS logic at the 22nm node and below is being done with a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes have been demonstrated using a “lines and cuts” approach with good pattern fidelity and process margin, with extendibility to ~7nm. In previous studies, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective down to the 12nm node.[2,3,4,5,6] The transition from single- to double- and in some cases triple- patterning was evaluated for different layout styles, with highly regular layouts delaying the need for multiple-patterning compared to complex layouts. To address mask complexity and cost, OPC for the “cut” patterns was studied and relatively simple OPC was found to provide good quality metrics such as MEEF and DOF.[3,7,8] This is significant since mask data volumes of >500GB per layer are projected for pixelated masks created by complex OPC or inverse lithography; writing times for such masks are nearly prohibitive. In our present work, we extend the scaling using SMO with “OPC Lite” beyond 12nm. The focus is on the contact pattern since a “hole” pattern is similar to a “cut” pattern so a similar technique should be useful. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous studies. The contact pattern is a relatively dense layer since it connects two underlying layers – active and gate – to one overlying layer – metal-1. Several design iterations were required to get suitable layouts while maintaining circuit functionality. Experimental demonstration of the contact pattern using OPC-Lite will be presented. Wafer results have been obtained at a metal-1 half-pitch of 18nm, corresponding to the 11nm CMOS node. Additional results for other layers – FINs, local interconnect, and metal-1 – will also be discussed.