31 March 2014 A generalized edge-placement yield model for the cut-hole patterning process
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Abstract
A generalized edge-placement yield model for the cut-hole patterning process is developed. It incorporates the cut-hole overlay errors, cut-hole and grating line/space CD variations into a unified physical model to investigate the key parameters that affect the edge-placement yield. The yield related features are identified first and probability-of-failure (POF) functions are introduced to construct the yield formula. The variable number in the yield integral is reduced from four to two by a special transformation method. Our calculation results show that the cut-hole overhang and (grating) line/space CD must be optimized in order to achieve the maximum yield. The sensitivity of edge-placement yield to various statistical parameters is investigated and the overlay errors are found to play a dominant role. We also study the scaling trend of the edge-placement yield and show that non-trivial challenges of manufacturing (half-pitch) 7-nm FinFET devices will require significantly improved overlay accuracy and process control.
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Pan Zhang, Chuyang Hong, Yijian Chen, "A generalized edge-placement yield model for the cut-hole patterning process", Proc. SPIE 9052, Optical Microlithography XXVII, 90521Q (31 March 2014); doi: 10.1117/12.2046437; https://doi.org/10.1117/12.2046437
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