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28 March 2014 Demonstrating production quality multiple exposure patterning aware routing for the 10NM node
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Abstract
This paper reviews the escalation in design constraints imposed on 2nd level wiring by multiple patterning exposure techniques in the 10NM technology node (i.e. ~45nm wiring pitch) relative to the 14NM technology node (i.e. 64nm wiring pitch). Specifically, new challenges facing place-and-route tooling are outlined, solutions to overcome these challenges are reviewed, and a manufacturing ready implementation is demonstrated.
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Lars Liebmann, Vassilios Gerousis, Paul Gutwin, Mike Zhang, Geng Han, and Brian Cline "Demonstrating production quality multiple exposure patterning aware routing for the 10NM node", Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 905309 (28 March 2014); https://doi.org/10.1117/12.2045958
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