28 March 2014 Layout induced variability and manufacturability checks in FinFETs process
Author Affiliations +
Abstract
With increasing chip sizes and shrinking device dimensions, on-chip semiconductor process variation can no longer be ignored in the design and signoff static timing analysis of integrated circuits. An important parameter affecting CMOS technologies is the gate length (Lgate) of a transistor. In modern technologies significant spatial intra-chip variability of transistor gate lengths which are systematic, as opposed to random, can lead to relatively large variations in circuit path delays. Spatial variations in Lgate affect circuit timing properties, which can lead to timing errors and performance loss. To maximize performance and process utilization in microprocessor designs, we have developed and validated a timing analysis methodology based on accurate silicon contour prediction from drawn layout and contour-based extraction of our designs. This allows for signoff timing without unnecessarily large margins, thereby reducing chip area and maximizing performance while ensuring chip functionality, improved process utilization and yield. In this paper we describe such a chip timing methodology, its validation and implementation in microprocessor design. We also report results of layout optimization based on new pattern matching technology.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Yongchan Ban, Yongchan Ban, Jason Sweis, Jason Sweis, Philippe Hurat, Philippe Hurat, Ya-Chieh Lai, Ya-Chieh Lai, Yongseok Kang, Yongseok Kang, Woo Hyun Paik, Woo Hyun Paik, Wei Xu, Wei Xu, Huiyuan Song, Huiyuan Song, } "Layout induced variability and manufacturability checks in FinFETs process", Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530I (28 March 2014); doi: 10.1117/12.2046284; https://doi.org/10.1117/12.2046284
PROCEEDINGS
7 PAGES


SHARE
RELATED CONTENT

The prospects of design for roll to roll lithography ...
Proceedings of SPIE (March 28 2014)
A state of the art hotspot recognition system for full...
Proceedings of SPIE (April 04 2011)
Manufacturing challenges for sub-half-micron technologies
Proceedings of SPIE (September 19 1995)
The end of the semiconductor industry as we know it
Proceedings of SPIE (June 16 2003)
Designing to win in sub-90nm mask production
Proceedings of SPIE (November 07 2005)
DfM, the teenage years
Proceedings of SPIE (March 19 2008)

Back to Top