28 March 2014 Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip)
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Abstract
An AC current induced electromigration (EM) on clock and logic signals becomes a significant problem even in the presence of reverse-recovery effect. Compared to power network, clock and logic signal interconnects are much narrower (mostly drawn up to the minimum width and space) and suffer from fast switching and large driving current from FinFETs. Thus, the high current density on those signal interconnects can cause a serious failure. In this paper, we analyse EM on signal interconnects in 16nm FinFET design, and characterize the impact of process variations, e.g., lithography and etch process, CMP (chemical-mechanical polishing) process, redundant via, etc. Then we optimize the signal lines with various design approaches to mitigate EM problem in 16nm design.
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Yongchan Ban, Yongchan Ban, Changseok Choi, Changseok Choi, Hosoon Shin, Hosoon Shin, Yongseok Kang, Yongseok Kang, Woo Hyun Paik, Woo Hyun Paik, } "Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip)", Proc. SPIE 9053, Design-Process-Technology Co-optimization for Manufacturability VIII, 90530P (28 March 2014); doi: 10.1117/12.2046207; https://doi.org/10.1117/12.2046207
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