24 June 2014 Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing
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Abstract
A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined processing of row and column image data prior to off chip readout reduces the required output bandwidth of the image sensor, thus reducing the latency of computations necessary to implement various image processing systems. Data volume reductions of over 80% lead to sub 10μs latency for completing various tracking and sensor algorithms. This paper details the architecture of the pixel-processing imager (PPI) and presents some initial results from a prototype device fabricated in a standard 65nm CMOS process hybridized to a commercial off-the-shelf short-wave infrared (SWIR) detector array.
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Jeffrey W. Little, Jeffrey W. Little, Brian M. Tyrrell, Brian M. Tyrrell, Richard D'Onofrio, Richard D'Onofrio, Paul J. Berger, Paul J. Berger, Christy Fernandez-Cull, Christy Fernandez-Cull, } "Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing", Proc. SPIE 9070, Infrared Technology and Applications XL, 90703B (24 June 2014); doi: 10.1117/12.2057519; https://doi.org/10.1117/12.2057519
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