21 May 2014 Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics
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Abstract
Over the past decade, the development of infrared focal plane arrays (FPAs) has seen two trends: decreasing of the pixel size and increasing of signal-processing capability at the device level. Enabling more capability within smaller pixels can be achieved through the use of advanced wafer-level processes for the integration of FPAs with silicon (Si) readout integrated circuits (ROICs). In this paper, we review the development of these wafer-level integration technologies, highlighting approaches in which the infrared sensor is integrated with three-dimensional ROIC stacks composed of multiple layers of Si circuitry interconnected using metal-filled through-silicon vias.
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Dorota S. Temple, Dorota S. Temple, Erik P. Vick, Erik P. Vick, Matthew R Lueck, Matthew R Lueck, Dean Malta, Dean Malta, Mark R. Skokan, Mark R. Skokan, Christopher M. Masterjohn, Christopher M. Masterjohn, Mark S. Muzilla, Mark S. Muzilla, } "Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics", Proc. SPIE 9100, Image Sensing Technologies: Materials, Devices, Systems, and Applications, 91000L (21 May 2014); doi: 10.1117/12.2054106; https://doi.org/10.1117/12.2054106
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