Paper
25 July 2014 VERITAS 2.0 a multi-channel readout ASIC suitable for the DEPFET arrays of the WFI for Athena
Matteo Porro, Davide Bianchi, Giulio De Vita, Sven Herrmann, Andreas Wassatsch, Alexander Bähr, Bettina Bergbauer, Norbert Meidinger, Sabine Ott, Johannes Treis
Author Affiliations +
Abstract
VERITAS 2.0 is a multi-channel readout ASIC for pnCCDs and DEPFET arrays. The main chip application is the readout of the DEPFET pixel arrays of the Wide Field Imager for the Athena mission. Every readout channel implements a trapezoidal weighting function and it is based on a fully differential architecture. VERITAS 2.0 is the first ASIC able to readout the DEPFETs both in source follower mode and in drain current mode. The drain readout should make it possible to achieve a processing time of about 2-3 μs/line with an electronics noise ≤ 5 electrons r.m.s.. The main concept and first measurements are presented.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Matteo Porro, Davide Bianchi, Giulio De Vita, Sven Herrmann, Andreas Wassatsch, Alexander Bähr, Bettina Bergbauer, Norbert Meidinger, Sabine Ott, and Johannes Treis "VERITAS 2.0 a multi-channel readout ASIC suitable for the DEPFET arrays of the WFI for Athena", Proc. SPIE 9144, Space Telescopes and Instrumentation 2014: Ultraviolet to Gamma Ray, 91445N (25 July 2014); https://doi.org/10.1117/12.2056097
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Cited by 18 scholarly publications.
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KEYWORDS
Field effect transistors

Sensors

Electrons

Analog electronics

Electronics

Prototyping

Spectroscopy

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