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16 April 2014 A reconfigurable ASIP for high-throughput and flexible FFT processing in SDR environment
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Proceedings Volume 9159, Sixth International Conference on Digital Image Processing (ICDIP 2014); 91590M (2014) https://doi.org/10.1117/12.2064164
Event: Sixth International Conference on Digital Image Processing, 2014, Athens, Greece
Abstract
This paper presents a high-throughput and reconfigurable processor for fast Fourier transformation (FFT) processing based on SDR methodology. It adopts application specific instruction-set (ASIP) and single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. Moreover, a novel 3-dimension multi-bank memory is proposed for parallel conflict-free accesses. The overall throughput and power-efficiency are greatly enhanced by parallel and streamline processing. A test chip supporting 64~2048-point FFT is setup for experiment. Logic synthesis reveals a maximum clock frequency of 500MHz and an area of 0.49 mm2 for the processor's logic using a low power 45-nm technology, and the dynamic power estimation is about 96.6mW. Compared with previous works, our FFT ASIP achieves a higher energy-efficiency with relative low area cost.
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Ting Chen, Hengzhu Liu, and Botao Zhang "A reconfigurable ASIP for high-throughput and flexible FFT processing in SDR environment", Proc. SPIE 9159, Sixth International Conference on Digital Image Processing (ICDIP 2014), 91590M (16 April 2014); https://doi.org/10.1117/12.2064164
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