16 April 2014 The analysis and design of high speed double delta sampling circuit for CMOS image sensor
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Proceedings Volume 9159, Sixth International Conference on Digital Image Processing (ICDIP 2014); 91590P (2014) https://doi.org/10.1117/12.2064181
Event: Sixth International Conference on Digital Image Processing, 2014, Athens, Greece
Abstract
A high-speed double delta sampling (DDS) circuit with pipelined structure for CMOS image sensor (CIS) is presented. Considering the low readout speed of the DDS circuit compare with correcting double sampling (CDS) circuit, We separate the main operation of DDS circuit into two steps, and run the two steps alternately in odd readout column and even readout column, which seems like the pipelined operation. Thus, the readout speed of the DDS will as twice as fast than the traditional DDS. The architecture and readout sequence of the new circuit are introduced in detail. Meanwhile simulation results indicate the proposed circuit can achieve a high speed performance.
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Xiaohui Liu, Xiaohui Liu, Yuanfu Zhao, Yuanfu Zhao, Liyan Liu, Liyan Liu, Chunfang Wang, Chunfang Wang, Xiaofeng Jin, Xiaofeng Jin, Yue Zhao, Yue Zhao, } "The analysis and design of high speed double delta sampling circuit for CMOS image sensor", Proc. SPIE 9159, Sixth International Conference on Digital Image Processing (ICDIP 2014), 91590P (16 April 2014); doi: 10.1117/12.2064181; https://doi.org/10.1117/12.2064181
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