5 September 2014 Line-edge roughness and the impact of stochastic processes on lithography scaling for Moore's Law
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Abstract
Moore’s Law, the idea that every two years or so chips double in complexity and the cost of a transistor is always in decline, has been the foundation of the semiconductor industry for nearly 50 years. The main technical force behind Moore’s Law has been lithography scaling: shrinking of lithographic features at a rate faster than the increase in finished wafer costs. With smaller feature size comes the need for better control of those sizes during manufacturing. Critical dimension and overlay control must scale in proportion to feature size, and has done so for the last 50 years. But in the sub-50-nm feature size regime, a new problem has arisen: line-edge roughness due to the stochastic nature of the lithography process. Despite significant effort, this line-edge roughness has not scaled in proportion to feature size and is thus consuming an ever larger fraction of the feature size control budget. Projection of current trends predicts a collision course between lithography scaling needs and line-edge roughness reality. In the end, stochastic uncertainty in lithography and its manifestation as line-edge roughness will prove the ultimate limiter of resolution in semiconductor manufacturing.
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Chris A. Mack, Chris A. Mack, } "Line-edge roughness and the impact of stochastic processes on lithography scaling for Moore's Law", Proc. SPIE 9189, Photonic Innovations and Solutions for Complex Environments and Systems (PISCES) II, 91890D (5 September 2014); doi: 10.1117/12.2059929; https://doi.org/10.1117/12.2059929
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