This paper describes an experimental method which led to a 1.2 micron polysilicon process with both a zero bias and near zero micron critical dimension shift over polysilicon topography. These results were attained using a single layer positive photoresist process and a 10X reduction stepper with a 0.28 NA/0.7 partial coherence factor/436nm lens system. The two phase experimental method used in this work included a pretargeting experiment followed by a three variable response surface analysis. In the pretargeting experiment, a standing wave curve over polysilicon steps was generated to find areas of converging exposure thresholds relative to changing resist thickness at the top and bottom of topography. This was done, so that later work, in this study, examined a suitable range of resist thicknesses which did not exhibit photospeed divergence resulting from thickness variations near a step causing improperly balanced standing wave conditions. The final phase of this method included a three level, three variable experimental design, where resist thickness, soft bake time and temperature were chosen as the initial critical parameters to be studied. The quadratic model used in this process optimization required a minimum of three levels to ascertain the curvilinear effects of the process. Initial optimization was done using the previously published function. P(X(1), X(2)...) = TIF(i) i=0 This function represents an overall optimization as defined by the product of normalized signal-to-noise ratios, F(i), for the set of responses for the process variables X(1), X(2) studied.1 In this work, the three responses monitored were linewidth shift over topography at 1.2 micron sizing, energy to size a 1.2 micron target, and lastly, the exposure latitude as defined by the tangent of the linewidth versus exposure curve at the 1.2 micron sizing target. Experimentally, pretargeting work was done by coating topographical polysilicon wafers with resist at varying spin speeds, hot plate baking, then exposing using a serpentine open-frame exposure matrix array. After track development, wafers were visually inspected and the minimum energy to clear the resist off the top and bottom of critical topography was monitored. Spin speeds which yielded best photospeed convergence over the polysilicon steps were then chosen for subsequent experimental design work. To do this work, nineteen polysilicon wafers with topography were coated and baked under varying randomized bake and resist thickness conditions. Each wafer was then patterned with five different exposure levels centered around the energy to size the 1.2 micron target sizing, at approximately 2.4 ET units.2 Then linewidth measurements in a CD cell, and top and bottom of a step were made using a SEM. Finally, after determining response values for each test element, process modeling and optimization was done using E-Chip.1, 3 In this study, the effect of resist thickness and soft bake conditions on linewidth control over relief surfaces is examined and a method for minimizing the degree of these effects is discussed. Also, the method is reviewed and recommendations for general use are made.