Imaging performance and challenges of 10nm and 7nm logic nodes with 0.33 NA EUV

Eelco van Setten; Guido Schiffelers; Eleni Psara; Dorothe Oorschot; Natalia Davydova; Jo Finders; Laurent Depre; Vincent Farys

doi:10.1117/12.2065945

17 October 2014 Imaging performance and challenges of 10nm and 7nm logic nodes with 0.33 NA EUV

Eelco van Setten, Guido Schiffelers, Eleni Psara, Dorothe Oorschot, Natalia Davydova, Jo Finders, Laurent Depre, Vincent Farys

Author Affiliations +

Proceedings Volume 9231, 30th European Mask and Lithography Conference; 923108 (2014) https://doi.org/10.1117/12.2065945
Event: 30th European Mask and Lithography Conference, 2014, Dresden, Germany

Abstract

The NXE:3300B is ASML’s third generation EUV system and has an NA of 0.33 and is positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full transmission. Multiple systems have been qualified and installed at customers. The NXE:3300B succeeds the NXE:3100 system (NA of 0.25), which has allowed customers to gain valuable EUV experience. It is expected that EUV will be adopted first for critical Logic layers at 10nm and 7nm nodes, such as Metal-1, to avoid the complexity of triple patterning schemes using ArF immersion. In this paper we will evaluate the imaging performance of (sub-)10nm node Logic M1 on the NXE:3300B EUV scanner. We will show the line-end performance of tip-to-tip and tip-to-space test features for various pitches and illumination settings and the performance enhancement obtained by means of a 1st round of OPC. We will also show the magnitude of local variations. The Logic M1 cell is evaluated at various critical features to identify hot spots. A 2nd round OPC model was calibrated of which we will show the model accuracy and ability to predict hot spots in the Logic M1 cell. The calibrated OPC model is used to predict the expected performance at 7nm node Logic using off-axis illumination at 16nm minimum half pitch. Initial results of L/S exposed on the NXE:3300B at 7nm node resolutions will be shown. An outlook is given to future 0.33 NA systems on the ASML roadmap with enhanced illuminator capabilities to further improve performance and process window.

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Eelco van Setten, Guido Schiffelers, Eleni Psara, Dorothe Oorschot, Natalia Davydova, Jo Finders, Laurent Depre, and Vincent Farys "Imaging performance and challenges of 10nm and 7nm logic nodes with 0.33 NA EUV", Proc. SPIE 9231, 30th European Mask and Lithography Conference, 923108 (17 October 2014); https://doi.org/10.1117/12.2065945

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