IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly
for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically
remain in the “requal” phase for extended, non-productive periods of time. The overall “requal” cycle time in which
reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold
until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles
can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields.
One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects.
Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each
additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects.
Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding
lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due
to lithographic uncertainty presents significant cycle time loss and increased production costs
An automatic defect analysis system (ADAS), which has been in fab production for numerous years, has been improved
to handle the new challenges of 14nm node automate reticle defect classification by simulating each defect’s printability
under the intended illumination conditions. In this study, we have created programmed defects on a production 14nm
node critical-layer reticle. These defects have been analyzed with lithographic simulation software and compared to the
results of both AIMS optical simulation and to actual wafer prints.