24 October 2014 A 3-D optoelectronic integration methodology utilizing CMOS post-backend process
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Abstract
The integration of optical devices and electronic integrated circuits (IC) is a main issue for optoelectronic convergence. In this work, a CMOS post-backend process flow is proposed to potentially achieve a 3-D monolithic optoelectronic integrated chip. The proposed integrated chip is composed of an IC die as electronic layer and a waveguide device layer as photonic layer above electronic layer. The photonic layer is fabricated by CMOS post-backend process with a temperature blow 450 ºC, which would do no harm to the performance of the CMOS ICs. We also fabricated Si3N4 mircoring add-drop filters on a bulk Si wafer. The cross-section of the waveguide is 400 nm × 1 μm, and the radius of microring is 30μm. Measured results match well with numerical simulations.
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Zan Zhang, Beiju Huang, Zanyun Zhang, Chuantong Cheng, Xurui Mao, Hongda Chen, "A 3-D optoelectronic integration methodology utilizing CMOS post-backend process", Proc. SPIE 9270, Optoelectronic Devices and Integration V, 92701H (24 October 2014); doi: 10.1117/12.2071504; https://doi.org/10.1117/12.2071504
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