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24 October 2014A 3-D optoelectronic integration methodology utilizing CMOS post-backend process
The integration of optical devices and electronic integrated circuits (IC) is a main issue for optoelectronic convergence.
In this work, a CMOS post-backend process flow is proposed to potentially achieve a 3-D monolithic optoelectronic
integrated chip. The proposed integrated chip is composed of an IC die as electronic layer and a waveguide device layer
as photonic layer above electronic layer. The photonic layer is fabricated by CMOS post-backend process with a
temperature blow 450 ºC, which would do no harm to the performance of the CMOS ICs. We also fabricated Si3N4
mircoring add-drop filters on a bulk Si wafer. The cross-section of the waveguide is 400 nm × 1 μm, and the radius of
microring is 30μm. Measured results match well with numerical simulations.