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17 November 2014 Timing design and image processing of CMOS sensor LUPA-4000 based on FPGA
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This article describes a method of the timing sequence design for CMOS image sensor LUPA-4000. A FPGA based imaging system with the function of adjustable integration time, multiple-slope integration, parallel integration an reading, windowing readout has been designed. This design can satisfy the frequency of 66M limit frequency of LUPA-4000 and 20 frames of a second. As the fixed noise of LUPA-4000 is aloud and the image is not clear, an efficient real-time image processing algorithm is also described in this paper. First a black image should be acquired as the fixed noise image. The real-time images can be send out after subtracting the noise image. This method can effectively eliminate the fixed noise o f the image, as the same time, the original image information has been maintained in the maximum degree. The test experiments on FPGA shows this design can drive LUPA-4000 working properly. Also this design takes full advantage of the accessibility features of the device, which provides a wider dynamic range and more flexible application of the device. The image sensor driven by this design improves imaging quality, which can be used for space exploration, especially for small space dynamic target tracking.
© (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Li Xin "Timing design and image processing of CMOS sensor LUPA-4000 based on FPGA", Proc. SPIE 9279, Real-time Photonic Measurements, Data Management, and Processing, 92790Z (17 November 2014);

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