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27 February 2015 Toward new design-rule-check of silicon photonics for automated layout physical verifications
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Proceedings Volume 9367, Silicon Photonics X; 93671K (2015) https://doi.org/10.1117/12.2078357
Event: SPIE OPTO, 2015, San Francisco, California, United States
Abstract
A simple analytical model is developed to estimate the power loss and time delay in photonic integrated circuits fabricated using SOI standard wafers. This model is simple and can be utilized in physical verification of the circuit layout to verify its feasibility for fabrication using certain foundry specifications. This model allows for providing new design rules for the layout physical verification process in any electronic design automation (EDA) tool. The model is accurate and compared with finite element based full wave electromagnetic EM solver. The model is closed form and circumvents the need to utilize any EM solver for verification process. As such it dramatically reduces the time of verification process and allows fast design rule check.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Mohamed Ismail, Raghi S. El Shamy, Kareem Madkour, Sherif Hammouda, and Mohamed A. Swillam "Toward new design-rule-check of silicon photonics for automated layout physical verifications", Proc. SPIE 9367, Silicon Photonics X, 93671K (27 February 2015); https://doi.org/10.1117/12.2078357
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Cited by 1 scholarly publication.
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KEYWORDS
Waveguides

Photonic integrated circuits

Wave propagation

Silicon photonics

Electronic design automation

Instrument modeling

Semiconducting wafers

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