7 February 2015 FPGA implementation of high-performance QC-LDPC decoder for optical communications
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Forward error correction is as one of the key technologies enabling the next-generation high-speed fiber optical communications. Quasi-cyclic (QC) low-density parity-check (LDPC) codes have been considered as one of the promising candidates due to their large coding gain performance and low implementation complexity. In this paper, we present our designed QC-LDPC code with girth 10 and 25% overhead based on pairwise balanced design. By FPGAbased emulation, we demonstrate that the 5-bit soft-decision LDPC decoder can achieve 11.8dB net coding gain with no error floor at BER of 10-15 avoiding using any outer code or post-processing method. We believe that the proposed single QC-LDPC code is a promising solution for 400Gb/s optical communication systems and beyond.
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Ding Zou, Ding Zou, Ivan B. Djordjevic, Ivan B. Djordjevic, "FPGA implementation of high-performance QC-LDPC decoder for optical communications", Proc. SPIE 9388, Optical Metro Networks and Short-Haul Systems VII, 93880P (7 February 2015); doi: 10.1117/12.2080735; https://doi.org/10.1117/12.2080735

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