13 March 2015 14-bit pipeline-SAR ADC for image sensor readout circuits
Author Affiliations +
Abstract
A two stage 14bit pipeline-SAR analog-to-digital converter includes a 5.5bit zero-crossing MDAC and a 9bit asynchronous SAR ADC for image sensor readout circuits built in 0.18um CMOS process is described with low power dissipation as well as small chip area. In this design, we employ comparators instead of high gain and high bandwidth amplifier, which consumes as low as 20mW of power to achieve the sampling rate of 40MSps and 14bit resolution.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Gengyun Wang, Gengyun Wang, Can Peng, Can Peng, Tianzhao Liu, Tianzhao Liu, Cheng Ma, Cheng Ma, Ning Ding, Ning Ding, Yuchun Chang, Yuchun Chang, } "14-bit pipeline-SAR ADC for image sensor readout circuits", Proc. SPIE 9403, Image Sensors and Imaging Systems 2015, 94030L (13 March 2015); doi: 10.1117/12.2083307; https://doi.org/10.1117/12.2083307
PROCEEDINGS
7 PAGES


SHARE
Back to Top