13 March 2015 Overlay and edge placement control strategies for the 7nm node using EUV and ArF lithography
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Abstract
In this paper we discuss edge placement error (EPE) for multi-patterning application and compare the EPE budget with the one for EUV single expose application case. These two patterning methods are candidate for the manufacturing of 10-nm and 7-nm logic semiconductor devices. EUV will enable 2D random pattern layout, while in the multi-patterning case a more restricted 1D design layout is needed. For the 1D design approach we discuss the patterning control spacer pitch division resulting in complex multi-layer alignment and EPE optimization strategies. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets. We use 10-nm node experimental data and extrapolate the error budgets towards the 7-nm technology node. The experimental data will be based on NXE:3300B and NXT:1960Bi/NXT:1970Ci exposure systems. The results are compared to the more straightforward alternative of using single expose patterning with EUV for all critical layers.
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Jan Mulkens, Jan Mulkens, Michael Hanna, Michael Hanna, Hannah Wei, Hannah Wei, Vidya Vaenkatesan, Vidya Vaenkatesan, Henry Megens, Henry Megens, Daan Slotboom, Daan Slotboom, } "Overlay and edge placement control strategies for the 7nm node using EUV and ArF lithography", Proc. SPIE 9422, Extreme Ultraviolet (EUV) Lithography VI, 94221Q (13 March 2015); doi: 10.1117/12.2085761; https://doi.org/10.1117/12.2085761
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