19 March 2015 Implementation of templated DSA for via layer patterning at the 7nm node
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In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). Insertion of DSA for IC fabrication is seriously considered for the 7nm node. At this node the DSA technology could alleviate costs for double patterning and limit the number of masks that would be required per layer. At imec multiple approaches for inserting DSA into the 7nm node are considered. One of the most straightforward approaches for implementation would be for via patterning through templated DSA (grapho-epitaxy), since hole patterns are readily accessible through templated hole patterning of cylindrical phase BCP materials. Here, the pre-pattern template is first patterned into a spin-on hardmask stack. After optimizing the surface properties of the template the desired hole patterns can be obtained by the BCP DSA process. For implementation of this approach to be implemented for 7nm node via patterning, not only the appropriate process flow needs to be available, but also appropriate metrology (including for pattern placement accuracy) and DSA-aware mask decomposition are required. In this paper the imec approach for 7nm node via patterning will be discussed.
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Roel Gronheid, Roel Gronheid, Jan Doise, Jan Doise, Joost Bekaert, Joost Bekaert, Boon Teik Chan, Boon Teik Chan, Ioannis Karageorgos, Ioannis Karageorgos, Julien Ryckaert, Julien Ryckaert, Geert Vandenberghe, Geert Vandenberghe, Yi Cao, Yi Cao, Guanyang Lin, Guanyang Lin, Mark Somervell, Mark Somervell, Germain Fenger, Germain Fenger, Daisuke Fuchimoto, Daisuke Fuchimoto, "Implementation of templated DSA for via layer patterning at the 7nm node", Proc. SPIE 9423, Alternative Lithographic Technologies VII, 942305 (19 March 2015); doi: 10.1117/12.2086090; https://doi.org/10.1117/12.2086090

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