19 March 2015 Toward high-performance quality meeting IC device manufacturing requirements with AZ SMART DSA process
Author Affiliations +
Abstract
Significant progresses on 300 mm wafer level DSA (Directed Self-Assembly) performance stability and pattern quality were demonstrated in recent years. DSA technology is now widely regarded as a leading complementary patterning technique for future node integrated circuit (IC) device manufacturing. We first published SMARTTM DSA flow in 2012. In 2013, we demonstrated that SMARTTM DSA pattern quality is comparable to that generated using traditional multiple patterning technique for pattern uniformity on a 300 mm wafer. In addition, we also demonstrated that less than 1.5 nm/3σ LER (line edge roughness) for 16 nm half pitch DSA line/space pattern is achievable through SMARTTM DSA process. In this publication, we will report impacts on SMARTTM DSA performances of key pre-pattern features and processing conditions. 300mm wafer performance process window, CD uniformity and pattern LER/LWR after etching transfer into carbon-hard mask will be discussed as well.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
JiHoon Kim, JiHoon Kim, Jian Yin, Jian Yin, Yi Cao, Yi Cao, YoungJun Her, YoungJun Her, Claire Petermann, Claire Petermann, Hengpeng Wu, Hengpeng Wu, Jianhui Shan, Jianhui Shan, Tomohiko Tsutsumi, Tomohiko Tsutsumi, Guanyang Lin, Guanyang Lin, } "Toward high-performance quality meeting IC device manufacturing requirements with AZ SMART DSA process", Proc. SPIE 9423, Alternative Lithographic Technologies VII, 94230R (19 March 2015); doi: 10.1117/12.2086160; https://doi.org/10.1117/12.2086160
PROCEEDINGS
17 PAGES


SHARE
RELATED CONTENT

Driving DSA into volume manufacturing
Proceedings of SPIE (March 20 2015)
Template affinity role in CH shrink by DSA planarization
Proceedings of SPIE (March 19 2015)
Manufacturability considerations for DSA
Proceedings of SPIE (March 27 2014)
DSA via hole shrink for advanced node applications
Proceedings of SPIE (April 04 2016)

Back to Top