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19 March 2015 Toward high-performance quality meeting IC device manufacturing requirements with AZ SMART DSA process
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Significant progresses on 300 mm wafer level DSA (Directed Self-Assembly) performance stability and pattern quality were demonstrated in recent years. DSA technology is now widely regarded as a leading complementary patterning technique for future node integrated circuit (IC) device manufacturing. We first published SMARTTM DSA flow in 2012. In 2013, we demonstrated that SMARTTM DSA pattern quality is comparable to that generated using traditional multiple patterning technique for pattern uniformity on a 300 mm wafer. In addition, we also demonstrated that less than 1.5 nm/3σ LER (line edge roughness) for 16 nm half pitch DSA line/space pattern is achievable through SMARTTM DSA process. In this publication, we will report impacts on SMARTTM DSA performances of key pre-pattern features and processing conditions. 300mm wafer performance process window, CD uniformity and pattern LER/LWR after etching transfer into carbon-hard mask will be discussed as well.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
JiHoon Kim, Jian Yin, Yi Cao, YoungJun Her, Claire Petermann, Hengpeng Wu, Jianhui Shan, Tomohiko Tsutsumi, and Guanyang Lin "Toward high-performance quality meeting IC device manufacturing requirements with AZ SMART DSA process", Proc. SPIE 9423, Alternative Lithographic Technologies VII, 94230R (19 March 2015);


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