19 March 2015 Hybrid overlay metrology with CDSEM in a BEOL patterning scheme
Author Affiliations +
Abstract
Overlay metrology accuracy is a major concern for our industry. Advanced logic process require more tighter overlay control for multipatterning schemes. TIS (Tool Induced Shift) and WIS (Wafer Induced Shift) are the main issues for IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). Methods of compensation have been introduced, some are even very efficient to reduce these measured offsets. Another related question is about the overlay target designs. These targets are never fully representative of the design rules, strong efforts have been achieved, but the device cannot be completely duplicated. Ideally, we would like to measure in the device itself to verify the real overlay value. Top down CDSEM can measure critical dimensions of any structure, it is not dependent of specific target design. It can also measure the overlay errors but only in specific cases like LELE (Litho Etch Litho Etch) after final patterning. In this paper, we will revisit the capability of the CDSEM at final patterning by measuring overlay in dedicated targets as well as inside a logic and an SRAM design. In the dedicated overlay targets, we study the measurement differences between design rules gratings and relaxed pitch gratings. These relaxed pitch which are usually used in IBO or DBO targets. Beyond this “simple” LELE case, we will explore the capability of the CDSEM to measure overlay even if not at final patterning, at litho level. We will assess the hybridization of DBO and CDSEM for reference to optical tools after final patterning.

We will show that these reference data can be used to validate the DBO overlay results (correctables and residual fingerprints).
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Philippe Leray, Christiane Jehoul, Osamu Inoue, Yutaka Okagawa, "Hybrid overlay metrology with CDSEM in a BEOL patterning scheme", Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 942408 (19 March 2015); doi: 10.1117/12.2087116; https://doi.org/10.1117/12.2087116
PROCEEDINGS
8 PAGES


SHARE
RELATED CONTENT

Analyzing block placement errors in SADP patterning
Proceedings of SPIE (March 21 2016)
EPE analysis of sub N10 BEoL flow with and without...
Proceedings of SPIE (March 28 2017)
Wafer edge overlay control solution for N7 and beyond
Proceedings of SPIE (March 20 2018)
Double patterning compliant logic design
Proceedings of SPIE (April 04 2011)
Solutions for 22-nm node patterning using ArFi technology
Proceedings of SPIE (April 05 2011)

Back to Top