19 March 2015 Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes
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The semiconductor industry continues to push the limits of immersion lithography through multiple patterning techniques for printing features with critical dimension 20 nm and below. As a result overlay has become one of the critical lithography control parameters impacting device performance and has a stringent budget for yielding at smaller half pitch nodes. Overlay has several sources of errors related to scanner, lens, mask, and wafer. Lithographers have developed both linear and higher order field and wafer models to successfully compensate for the static fingerprints from different sources of error. After the static modeled portion of the fingerprint is removed, the remaining overlay error can be characterized as unstable modeled error or un-modeled error, commonly called uncorrectable residual error. This paper explores the fundamental relationship of overlay to wafer geometry through mechanisms of process-induced contributions to the wafer overlay, categorized as plastic and elastic wafer deformation. Correlation of overlay to local features such as slip lines is proven experimentally. The paper describes methodologies and geometry-induced overlay metrics for the application of wafer geometry to perform overlay feedback and feed forward applications. Feedback applications allow for process development and controlling semiconductor processes through in-line monitoring of wafers. Feed forward applications could include geometrybased corrections to the scanner for compensating non-static wafer geometry related overlay errors, and grouping wafers based on higher-order geometry.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Joel Peterson, Joel Peterson, Gary Rusk, Gary Rusk, Sathish Veeraraghavan, Sathish Veeraraghavan, Kevin Huang, Kevin Huang, Telly Koffas, Telly Koffas, Peter Kimani, Peter Kimani, Jaydeep Sinha, Jaydeep Sinha, "Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes", Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 94240N (19 March 2015); doi: 10.1117/12.2086525; https://doi.org/10.1117/12.2086525

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