Scatterometry mark design for improvement of the metrology performance is investigated in this joint work by
ASML and STMicroelectronics. The studied marks are small, enabling metrology within the device area. The new
mark-design approach reduces the effects from the mark-edges during the metrology measurement. For this, small
assist-features are integrated in the mark design on the wafer. Thereby the new designs: 1. enlarge the metrology
measurement-window, 2. optimize the repeatability and accuracy of the metrology at given mark size, 3. allow
added functionality to existing marks within the current mark area, such as monitoring process asymmetry or
multiple layer information, 4. allow for mark miniaturization at equal performance, enabling intra-field positioning.
With this metrology tool-optical proximity correction (MT-OPC) included in the mark design, the metrology window
is enhanced, while improved on-product overlay performance is obtained.