19 March 2015 Improving full-wafer on-product overlay using computationally designed process-robust and device-like metrology targets
Author Affiliations +
Abstract
In order to handle the upcoming 1x DRAM overlay and yield requirements, metrology needs to evolve to more accurately represent product device patterns while being robust to process effects. One way to address this is to optimize the metrology target design. A viable solution needs to address multiple challenges. The target needs to be resistant to process damage. A single target needs to measure overlay between two or more layers. Targets need to meet design rule and depth of focus requirements under extreme illumination conditions. These must be achieved while maintaining good precision and throughput with an ultra-small target. In this publication, a holistic approach is used to address these challenges, using computationally optimized metrology targets with an advanced overlay control loop.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Young-Sik Kim, Young-Sik Kim, Young-Sun Hwang, Young-Sun Hwang, Mi-Rim Jung, Mi-Rim Jung, Ji-Hwan Yoo, Ji-Hwan Yoo, Won-Taik Kwon, Won-Taik Kwon, Kevin Ryan, Kevin Ryan, Paul Tuffy, Paul Tuffy, Youping Zhang, Youping Zhang, Sean Park, Sean Park, Nang-Lyeom Oh, Nang-Lyeom Oh, Chris Park, Chris Park, Mir Shahrjerdy, Mir Shahrjerdy, Roy Werkman, Roy Werkman, Kyu-Tae Sun, Kyu-Tae Sun, Jin-Moo Byun, Jin-Moo Byun, } "Improving full-wafer on-product overlay using computationally designed process-robust and device-like metrology targets", Proc. SPIE 9424, Metrology, Inspection, and Process Control for Microlithography XXIX, 942414 (19 March 2015); doi: 10.1117/12.2085645; https://doi.org/10.1117/12.2085645
PROCEEDINGS
11 PAGES


SHARE
Back to Top