This report presents a model to predict, analyze, and monitor pattern edge placements errors occurring during integrated circuit manufacture. The edge placement errors are driven by overlay and imaging capabilities of scanners and pattering tools. The model can be used to analyze the impact of various imaging strategies on pattern placement statistics of layers composing ICs. Such analysis is essential to both, IC designers and lithography engineers, striving to successfully fabricate complex designs at economical manufacture yields. The report discusses key contributors to the image edge placement errors and presents examples of edge placement predictions based on scanner records. The edge placement error examples presented in this report are based on scanner overlay and CD uniformity performance for the current generation of integrated circuit designs.