In this study, lower blind contact immunity was observed for peripheral contacts comparing to the array contacts especially around wafer edge region. In order to overcome this problem, a series of investigations have been carried out. The wafer edge leveling optimization through circuit dependent focus edge clearance (CDFEC) option doesn’t get improvement. Air gauge improved process leveling (AGILE) function of ASML immersion scanner doesn’t show improved result either. The ILD uniformity improvement and step height treatments around wafer edge such as edge exclusion of film deposition and bevel etching are also ineffective to mitigate the blind contact problem of peripheral patterns. Altering the etch hard-mask stack is finally found to be an effective approach to alleviate the issue. For instance, through either containing high temperature deposition advanced patterning film (APF) in the hard-mask or inserting higher opaque film such as amorphous Si in between the hard-mask stack.
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