18 March 2015 DTCO at N7 and beyond: patterning and electrical compromises and opportunities
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Abstract
At 7nm and beyond, designers need to support scaling by identifying the most optimal patterning schemes for their designs. Moreover, designers can actively help by exploring scaling options that do not necessarily require aggressive pitch scaling. In this paper we will illustrate how MOL scheme and patterning can be optimized to achieve a dense SRAM cell; how optimizing device performance can lead to smaller standard cells; how the metal interconnect stack needs to be adjusted for unidirectional metals and how a vertical transistor can shift design paradigms. This paper demonstrates that scaling has become a joint design-technology co-optimization effort between process technology and design specialists, that expands beyond just patterning enabled dimensional scaling.
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Julien Ryckaert, Praveen Raghavan, Pieter Schuddinck, Huynh Bao Trong, Arindam Mallik, Sushil S. Sakhare, Bharani Chava, Yasser Sherazi, Philippe Leray, Abdelkarim Mercha, Jürgen Bömmels, Gregory R. McIntyre, Kurt G. Ronse, Aaron Thean, Zsolt Tökei, An Steegen, Diederik Verkest, "DTCO at N7 and beyond: patterning and electrical compromises and opportunities", Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270C (18 March 2015); doi: 10.1117/12.2178997; https://doi.org/10.1117/12.2178997
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