18 March 2015 Statistical modeling of SRAM yield performance and circuit variability
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Abstract
In this paper, we develop statistical models to investigate SRAM yield performance and circuit variability in the presence of self-aligned multiple patterning (SAMP) process. It is assumed that SRAM fins are fabricated by a positivetone (spacer is line) self-aligned sextuple patterning (SASP) process which accommodates two types of spacers, while gates are fabricated by a more pitch-relaxed self-aligned quadruple patterning (SAQP) process which only allows one type of spacer. A number of possible inverter and SRAM structures are identified and the related circuit multi-modality is studied using the developed failure-probability and yield models. It is shown that SRAM circuit yield is significantly impacted by the multi-modality of fins’ spatial variations in a SRAM cell. The sensitivity of 6-transistor SRAM read/write failure probability to SASP process variations is calculated and the specific circuit type with the highest probability to fail in the reading/writing operation is identified. Our study suggests that the 6-transistor SRAM configuration may not be scalable to 7-nm half pitch and more robust SRAM circuit design needs to be researched.
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Qi Cheng, Yijian Chen, "Statistical modeling of SRAM yield performance and circuit variability", Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270M (18 March 2015); doi: 10.1117/12.2085844; https://doi.org/10.1117/12.2085844
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