18 March 2015 Efficient etch bias compensation techniques for accurate on-wafer patterning
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Abstract
As technology development advances into deep submicron nodes, it is very important not to ignore any systematic effect that can impact CD uniformity and the final parametric yield. One important challenge for OPC is in choosing the proper etch process correction flow to compensate for design-to-design etch shrink variations. Although model-based etch compensation tools have been commercially available for a few years now, rules-based etch compensation tables have been the standard practice for several nodes. In our work, we study the limitations of the rules-based etch compensation versus model-based etch compensation. We study a 10nm process and provide the details of why using Model-Based Etch Process Correction can achieve up to 15% improvement in final CD uniformity. We also provide a systematic methodology for identifying the proper etch correction technique for a given etch process and assessing the potential accuracy gain when switching to the model-based etch correction.
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Mohamed Salama, Mohamed Salama, Ayman Hamouda, Ayman Hamouda, } "Efficient etch bias compensation techniques for accurate on-wafer patterning", Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270X (18 March 2015); doi: 10.1117/12.2085956; https://doi.org/10.1117/12.2085956
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