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18 March 2015 A holistic methodology to drive process window entitlement and its application to 20nm logic
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Early in a semiconductor node’s process development cycle, the technology definition is locked down using somewhat risky assumptions on what the process can deliver once it matures. In this early phase of the development cycle, detailed design rules start to be codified while the wafer patterning process is still being fine-tuned. As the process moves along the development cycle, and wafer processes are dialed-in, key yield improvement efforts focus on variability reduction. Design retargeting definitions are tweaked and finalized, and the use of finely tuned etch models to compensate for process bias are applied to accurately capture the more mature wafer process. The resulting mature patterning process is quite different from the one developed during the early stages of the technology definition. In this paper we describe an approach and flow to drive continuous improvement in the mask solution (OPC and MBSRAF) later in the process development and production readiness cycle stage. First, we establish the process window entitlement within the design-space by utilizing advanced mask optimization (MO) combined with the baseline process (i.e., model, etch compensation, and design retargeting). Second, gaps to the entitlement are used to identify and target issues with the existing OPC recipe and to drive continuous improvements to close these performance gaps across the critical design rules. We demonstrate this flow on a 20 nm contact layer.
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Lalit Shokeen, Ayman Hamouda, Mark Terry, Dan J. Dechene, Stephen Hsu, Michael Crouse, Pengcheng Li, Keith Gronlund, and Gary Zhang "A holistic methodology to drive process window entitlement and its application to 20nm logic", Proc. SPIE 9427, Design-Process-Technology Co-optimization for Manufacturability IX, 94270Z (18 March 2015);

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