Paper
17 March 2015 Patterning in the era of atomic scale fidelity
Thorsten Lill, Samantha Tan, Keren J. Kanarik, Yoshie Kimura, Gowri Kamarthy, Meihua Shen, Vahid Vahedi, Jeffrey Marks, Richard A. Gottscho
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Abstract
Relentless scaling of advanced integrated devices drives feature dimensions towards values which can be expressed in small multiples of the lattice spacing of silicon. One of the consequences of dealing with features on such an atomic scale is that surface properties start to play an increasingly important role. To encompass both dimensional as well as compositional and structural control, we introduce the term “atomic scale fidelity.” In this paper, we will discuss the challenges as well as new solutions to achieve atomic scale fidelity for patterning etch processes. Fidelity of critical dimensions (CD) across the wafer is improved by means of the Hydra Uniformity System. Wafer, chip and feature level atomic scale fidelity such as etch rate uniformity, aspect ratio dependent etching (ARDE) /1/, selectivity and surface damage can be addressed with emerging atomic layer etching (ALE) approaches /2/.
© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Thorsten Lill, Samantha Tan, Keren J. Kanarik, Yoshie Kimura, Gowri Kamarthy, Meihua Shen, Vahid Vahedi, Jeffrey Marks, and Richard A. Gottscho "Patterning in the era of atomic scale fidelity", Proc. SPIE 9428, Advanced Etch Technology for Nanopatterning IV, 942809 (17 March 2015); https://doi.org/10.1117/12.2178326
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Cited by 5 scholarly publications.
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KEYWORDS
Etching

Silicon

Optical lithography

Semiconducting wafers

Focus stacking software

Critical dimension metrology

Oxides

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